1. Field of the Invention
The present invention relates in general to an output buffer circuit for a memory device,.and more particularly to an output buffer circuit for a memory device in which two pairs of MOS transistors are complementarily connected-to each other, two charging paths are formed in one of the two pairs of MOS transistors and two discharging paths are formed in the other pair of MOS transistors, so that a load capacitance can charge or discharge along a desired one of the two charging paths and the two discharging paths according to a level of an output voltage.
2. Description of the Prior Art
Generally, a MOS memory device comprises a plurality of memory cells, each of which consists of a MOS transistor. The MOS transistors constitute a memory cell matrix. When a predetermined address signal and a predetermined read control signal are applied to the MOS memory device, desired data is read from the corresponding memory cell and then outputted through an output buffer circuit.
Such a conventional output buffer circuit comprises a pair of PMOS and NMOS transistors connected commonly at their drains in a complementary manner. The PMOS transistor has a source connected to a supply voltage and the NMOS transistor has a source connected to a ground voltage through a lead inductance by a bonding wire or a lead wire of a lead frame. As a result, as the PMOS and NMOS transistor's are operated in response to data signals applied to gates thereof, a final data signal is outputted from an output terminal connected to an intermediate junction point of the drains of the PMOS and NMOS transistors. On the other hand, a load capacitance is connected to the output terminal of the output buffer circuit. The load capacitance has a capacity based on a standard of the MOS memory device. When the load capacitance discharges through the lead inductance according to the operations of the PMOS and NMOS transistors, an induced voltage is generated in the lead inductance. However, such an induced voltage may vary reference voltages of other circuits connected to the memory cell matrix. Furthermore, in the case where a plurality of output buffers are coupled in one memory device, the induced voltages of the corresponding number are simultaneously generated, resulting in a high voltage of several hundred millivolts. For this reason, an output signal of the output buffer circuit is distorted due to an abrupt variation of the induced voltage.
Referring to FIG. 1, there is shown a circuit diagram of a conventional output buffer circuit having an induced voltage attenuating function. As shown in this drawing, the conventional output buffer circuit comprises an inverter 12 for inverting an output disable signal OD, a NANDgate 11 for NANDing a data signal and an output signal from the inverter 12, a first NOR gate 13 for NORing the data signal and the output disable signal OD, an inverter 14 for inverting the data signal, an inverter 15 for inverting an output signal from the inverter 14, a second NOR gate 13 for NORing an output signal from the inverter 15, the data signal and the output disable signal OD, and a PMOS transistor 17 for performing a switching operation. The PMOS transistor 17 has a gate connected to an output terminal of the NAND gate 11, a source connected to a supply voltage Vdd and a drain connected to a drain of a first NMOS transistor 18.
The first NMOS transistor 18 is adapted to perform a switching operation. To this end, the first NMOS transistor 18 has a gate connected to an output terminal of the first NOR gate 13, a source connected to a ground terminal through a lead inductance 19 and the drain connected to the drain of the PMOS transistor 17.
Further, the conventional output buffer circuit comprises a second NMOS transistor 20 for performing a switching operation. The second NMOS transistor 20 has a gate connected to an output terminal of the second NOR gate 16, a drain connected to the drain of the first NMOS transistor 18 and a source connected to the source of the first NMOS transistor 18.
The operation of the conventional output buffer circuit for the memory device with the above-mentioned construction will hereinafter be described.
First, when the output disable signal OD is high in logic, it is inverted into low logic and then applied to the NAND gate 11. As a result, the NAND gate 11 outputs a high logic signal regardless of the other input signal, thereby causing the PMOS transistor 17 to be turned off. Also, the first NOR gate 13 outputs a low logic signal regardless of the other input signal, thereby causing the first NMOS transistor 18 to be turned off. Similarly, the second NOR gate 16 outputs a low logic signal regardless of other input signals, thereby causing the second NMOS transistor 20 to be turned off. In result, in the case where the output disable signal OD is high in logic, the circuit is turned off and the output thereof is thus disabled.
When the output disable signal OD goes low in logic and the data signal goes high in logic, the output signal of the NAND gate 11 goes low in logic, thereby causing the PMOS transistor 17 to be turned on. On the contrary, the output signals of the first and second NOR gates 13 and 16 become low in logic, so that the first and second NMOS transistors 18 and 20 are turned off. As a result, the supply voltage Vdd is charged on a load capacitance C through the turned-on PMOS transistor 17. In result, an output voltage Vout at an output terminal becomes the same as the supply voltage Vdd.
In the case where the data signal is changed from its high logic to its low logic under the above condition, the output signal of the NAND gate 11 becomes high in logic, thereby causing the PMOS transistor 17 to be turned off. Because the output signal of the first NOR gate 13 goes high in logic, the first NMOS transistor 18 is turned on. The output signal of the second NOR gate 16 goes high in logic after a delay of a predetermined time period .tau. from the moment that the output signal of the first NOR gate 13 goes high in logic, since the data signal is sequentially inverted by the inverters 14 and 15. The predetermined time period .tau. corresponds to the sum of propagation delay times of the inverters 14 and 15. In result, the second NMOS transistor 20 is turned on after the lapse of the predetermined time period .tau. from the moment that the first NMOS transistor 18 is turned on.
Subsequently, a charge on the load capacitance C is first discharged through the first NMOS transistor 18. Then, the charge on the load capacitance C begins to be discharged through the second NMOS transistor 20 when the predetermined time period .tau. has elapsed. In this case, currents flowing through the first and second NMOS transistors 18 and 20 have waveforms as shown in FIGS. 2A and 2B, respectively. The current i18 flowing through the first NMOS transistor 18 has a peak value I1 for ON-time .DELTA.T1 as shown in FIG. 2A. As shown in FIG. 2B, the current i20 flowing through the second NMOS transistor 20 has a peak value I2 for ON-time .DELTA.T2 shorter by the predetermined time period r than that of the first NMOS transistor 18.
The total current iS flowing through the lead inductance 19 of the output buffer circuit is the sum of the current i18 flowing through the first NMOS transistor 18 and the current i20 flowing through the second NMOS transistor 20. As shown in FIG. 2C, the total current iS has the same peak value I1 as that of the first NMOS transistor 18 for ON-time .DELTA.T3.
In the conventional output buffer circuit, as mentioned above, the delay time t is adjustable by sizes of the first and second NMOS transistors 18 and 20 to lower a peak value of current resulting from an induced voltage generated in the lead inductance 19. Therefore, the conventional output buffer circuit can prevent a distortion of the output signal due to an abrupt variation of a peak voltage. However, in the conventional output buffer circuit, the first and second NMOS transistors 18 and 20 are nearly simultaneously turned on because the delay time must typically be 3-4 ns to maintain the operation at a high speed. For this reason, the current peak value cannot in practice be lowered as shown in FIG. 4.